The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Dec. 12, 2023
International Business Machines Corporation, Armonk, NY (US);
William Murphy Parkin, Troy, NY (US);
Susan Ng Emans, Albany, NY (US);
Julien Frougier, Albany, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Andrew M. Greene, Slingerlands, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the present disclosure are directed to co-integrating multiple fin heights with bottom dielectric isolations for effective width tuning. In a non-limiting embodiment, a semiconductor structure includes a first shallow trench isolation (STI) region formed over a first portion of a substrate and a second STI region formed over a second portion of the substrate. A topmost surface of the second STI region is coplanar to a topmost surface of the first STI region. A first fin is formed in the first STI region and a second fin is formed in the second STI region. A topmost surface of the second fin is coplanar to a topmost surface of the first fin. A bottom dielectric isolation (BDI) region is positioned between the first fin and the substrate, thereby providing a first effective width and a second effective width for the first fin and second fin, respectively.