The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

May. 09, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyojin Yun, Suwon-si, KR;

Unbyoung Kang, Suwon-si, KR;

Seokbong Park, Suwon-si, KR;

Sechul Park, Suwon-si, KR;

Junyoung Park, Suwon-si, KR;

Teahwa Jeong, Suwon-si, KR;

Juil Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H10W 70/60 (2026.01); H10W 70/67 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 70/688 (2026.01); H10W 74/131 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package includes a substrate including a first region, a second region in contact with the first region with the first and second regions stacked in a first direction, and a third region extending from the first and second regions in a second direction, perpendicular to the first direction, to connect the first and second regions to each other in bent form, a first semiconductor chip on a first side opposite to a second side of the first region in contact with the second region, a second semiconductor chip on a first side opposite to a second side of the second region in contact with the first region, a first molding member on the first region and covering at least a portion of the first semiconductor chip, and a second molding member on the second region and covering at least a portion of the second semiconductor chip.


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