The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jul. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tung-Ting Wu, Taipei City, TW;

Chen-Jong Wang, Hsin-Chu, TW;

Jen-Cheng Liu, Hsin-Chu City, TW;

Yimin Huang, Hsinchu City, TW;

Chin-Chia Kuo, Tainan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10F 39/00 (2025.01); H10F 39/12 (2025.01); H01L 23/58 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10F 39/024 (2025.01); H10F 39/199 (2025.01); H10F 39/807 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a plurality of semiconductor devices arranged on a substrate and within a device region. A first isolation structure is arranged in the device region and laterally between adjacent semiconductor devices in the plurality of semiconductor devices. An interconnect structure underlies the substrate and includes a topmost conductive interconnect element adjacent to the substrate. A second isolation structure is disposed in the substrate and around the device region. A bottom surface of the second isolation structure is above a lower surface of the topmost conductive interconnect element.


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