The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Aug. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hung-Pin Chang, New Taipei, TW;

Cheng-Hsien Hsieh, Kaohsiung, TW;

Li-Han Hsu, Hsinchu, TW;

Wei-Cheng Wu, Hsinchu, TW;

Der-Chyang Yeh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 74/014 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/794 (2026.01);
Abstract

In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.


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