The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Apr. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ko-Cheng Liu, Hsinchu City, TW;

Chang-Miao Liu, Hsinchu City, TW;

Huiling Shang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract

Semiconductor structures and methods are provided. In an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.


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