The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jun. 03, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hong Jiang, El Dorado Hills, CA (US);

Sabareesh Ganapathy, Santa Clara, CA (US);

Xinmin Tian, Fremont, CA (US);

Fangwen Fu, Folsom, CA (US);

James Valerio, North Plains, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3009 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 9/4881 (2013.01); G06F 9/522 (2013.01); G06T 1/20 (2013.01);
Abstract

Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU) coupled to the memory device. The GPU can be configured to: execute an instruction thread; determine if a signal barrier is associated with the instruction thread; for the signal barrier associated with the instruction thread, determine if the signal barrier is cleared; and based on the signal barrier being cleared, permit any waiting instruction thread associated with the signal barrier identifier to commence with execution but not permit any waiting thread that is not associated with the signal barrier identifier to commence with execution.


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