The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2026
Filed:
Feb. 28, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Leonard P. Guler, Hillsboro, OR (US);
Sukru Yemenicioglu, Portland, OR (US);
Mohit K. Haran, Forest Grove, OR (US);
Shengsi Liu, Portland, OR (US);
Robert Joachim, Beaverton, OR (US);
Dan S. Lavric, Portland, OR (US);
Stephen M. Cea, Hillsboro, OR (US);
Assignee:
INTEL CORPORATION, SANTA CLARA, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
U.S. Cl.
CPC ...
H10D 62/121 ; H10D 84/83 ; H10D 30/6757 ; H10D 64/258 ; H10D 30/019 ; H10D 84/0135 ; H10D 62/118 ; H10D 30/501 ; H10D 84/832 ; H10D 30/6735 ; H10D 84/038 ; H10D 84/0153 ; B82Y 10/00 ;
Guler, Leonard. (2026). Gate cut grid across integrated circuit (U.S. Patent No. 12713691). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12713691
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile