The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Chen-Shien Chen, Zhubei City, TW;

Chih-Hong Wang, Taipei City, TW;

Ting Hao Kuo, Hsinchu City, TW;

Yu-Chia Lai, Zhunan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 42/00 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 42/00 (2026.01); H10W 70/685 (2026.01); H10W 74/117 (2026.01); H10W 72/952 (2026.01); H10W 80/312 (2026.01); H10W 90/20 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor die includes lower dies separated by a dielectric region; a cross die vertically stacked on the lower dies and the dielectric region; a molding structure filling the dielectric region and surrounding side surfaces of the lower dies and the cross die; and a bonding ring connecting the cross die to the lower dies and including: an upper metal ring formed in a bottom surface of the cross die; and a lower metal ring formed in top surfaces of the lower dies and extending through the molding structure in the dielectric region. The lower metal ring is bonded to the upper metal ring.


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