The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Nov. 23, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu City, TW;

Kai-Chiang Wu, Hsinchu City, TW;

Chun-Lin Lu, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/09 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/614 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 74/017 (2026.01); H10W 74/117 (2026.01); H10W 74/121 (2026.01); H10W 74/129 (2026.01); H10W 90/00 (2026.01); H10W 70/63 (2026.01); H10W 72/241 (2026.01); H10W 72/874 (2026.01); H10W 72/9413 (2026.01); H10W 74/019 (2026.01); H10W 74/15 (2026.01); H10W 80/211 (2026.01); H10W 90/724 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.


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