The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

May. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu City, TW;

Tung-Liang Shao, Hsinchu City, TW;

Yu-Sheng Huang, Changhua County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2026.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H10P 72/70 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H10P 72/7402 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 72/07252 (2026.01); H10W 72/221 (2026.01); H10W 72/856 (2026.01); H10W 72/932 (2026.01);
Abstract

A package structure is provided. The package structure includes a cell chip structure having a memory cell and a multiplexer. The package structure includes an intermediate chip structure directly bonded to the cell chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding and having a sense amplifier and a driver element. The intermediate chip structure does not have a memory cell. The package structure includes a calculating chip structure bonded to the intermediate chip structure and having a calculating element.


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