The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Dec. 22, 2022
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract
The present disclosure provides a memory device having a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first set of peripheral circuits having a first transistor configured to operate with a first voltage, and a second set of peripheral circuits having a second transistor configured to operate with a second voltage lower than the first voltage. The second set of peripheral circuits are disposed over the first set of peripheral circuits. The second semiconductor structure includes memory cells coupled to the first semiconductor structure.