The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jun. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhihua Zou, Singapore, SG;

Omkar Karhade, Chandler, AZ (US);

Botao Zhang, Gilbert, AZ (US);

Julia Chiu, Portland, OR (US);

Vivek Chidambaram, Singapore, SG;

Yi Shi, Chandler, AZ (US);

Mohit Bhatia, Chandler, AZ (US);

Mostafa Aghazadeh, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/90 (2026.01); H10W 99/00 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 72/90 (2026.01); H10W 80/327 (2026.01); H10W 99/00 (2026.01); H10W 72/934 (2026.01); H10W 80/033 (2026.01); H10W 80/312 (2026.01); H10W 80/732 (2026.01); H10W 90/792 (2026.01);
Abstract

Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.


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