The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Apr. 06, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sanjay Dabral, Cupertino, CA (US);

Jun Zhai, Cupertino, CA (US);

Kunzhong Hu, Cupertino, CA (US);

Sivachandra Jangam, Milpitas, CA (US);

Zhitao Cao, Campbell, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10D 1/68 (2025.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10D 1/68 (2025.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01);
Abstract

Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.


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