The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Oct. 30, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chuan-Pu Chou, Hsinchu, TW;

Chia-Tien Wu, Hsinchu, TW;

Hsin-Ping Chen, Hsinchu, TW;

Wei-Chen Chu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/00 (2026.01); H10W 20/46 (2026.01); H10W 20/48 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/069 (2026.01); H10W 20/072 (2026.01); H10W 20/46 (2026.01); H10W 20/48 (2026.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.


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