The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Dec. 27, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Suddhasattwa Nad, Chandler, AZ (US);

Srinivas Pietambaram, Chandler, AZ (US);

Brandon Marin, Gilbert, AZ (US);

Jeremy Ecton, Gilbert, AZ (US);

Gang Duan, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/823 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/288 (2026.01); H10W 90/291 (2026.01); H10W 90/792 (2026.01);
Abstract

An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.


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