The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Mar. 25, 2022
Applicant:

Creeled, Inc., Durham, NC (US);

Inventors:

Timothy Ling, Raleigh, NC (US);

Ryan Mohn, Mebane, NC (US);

David N. Randolph, Wake Forest, NC (US);

David Peoples, Raleigh, NC (US);

Wooh Jae Kim, Cary, NC (US);

Assignee:

CreeLED, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10H 20/85 (2025.01); H10H 20/01 (2025.01); H10H 20/857 (2025.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10H 20/8506 (2025.01); H10W 70/65 (2026.01); H10W 72/07336 (2026.01); H10W 90/734 (2026.01);
Abstract

Semiconductor packages and more particularly mounting arrangements for semiconductor packages and related methods are disclosed. Mounting arrangements include metal pads on substrates and selectively placed solder material on various portions of the metal pads. Semiconductor packages may be initially positioned on the solder material and on portions of the metal pads. During solder reflow, the solder material may spread along portions of the metal pads that were previously uncovered by the solder material and effectively move the semiconductor packages. Specific arrangements of metal pad and selective solder material patterns may be provided that control directions of such movements during reflow. Resulting mounting positions of semiconductor packages may be provided with spacings that are closer than limits of pick and place equipment used to initially position the semiconductor packages.


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