The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Jan. 23, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Sin-Yao Huang, Tainan City, TW;

Ching-Chun Wang, Tainan, TW;

Dun-Nian Yaung, Taipei City, TW;

Feng-Chi Hung, Chu-Bei City, TW;

Ming-Tsong Wang, Taipei City, TW;

Shih Pei Chou, Tainan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/12 (2025.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10F 39/199 (2025.01); H10F 39/018 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01);
Abstract

Some embodiments relate an integrated circuit (IC) including a first substrate. An interconnect structure is disposed over the first substrate. The interconnect structure includes a plurality of metal features that are stacked over one another. A lowermost metal feature of the plurality of metal features is closest to the first substrate, an uppermost metal feature of the plurality of metal features is furthest from the first substrate, and intermediate metal features are disposed between the lowermost metal feature and the uppermost metal feature. A recess extends into the interconnect structure and terminates at a bond pad. A lower surface of the bond pad directly contacts an upper surface of the lowermost metal feature.


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