The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Oct. 24, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Tom Herrmann, Dresden, DE;

Zhixing Zhao, Dresden, DE;

Alban Zaka, Dresden, DE;

Yiching Chen, San Jose, CA (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/00 (2025.01); H10D 30/63 (2025.01); H10D 62/10 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 86/201 (2025.01); H10D 30/637 (2025.01); H10D 62/116 (2025.01); H10D 86/01 (2025.01);
Abstract

A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.


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