The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Jul. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Lo-Heng Chang, Hsinchu, TW;

Yu-Xuan Huang, Hsinchu City, TW;

Lin-Yu Huang, Hsinchu, TW;

Huan-Chieh Su, Changhua County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10P 50/28 (2026.01);
U.S. Cl.
CPC ...
H10D 64/015 (2025.01); H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10P 50/282 (2026.01); H10D 30/6757 (2025.01);
Abstract

A method includes forming first semiconductor layers vertically stacked over a substrate; forming a gate structure over the first semiconductor layers; etching portions of the first semiconductor layers and the substrate uncovered by the substrate to form recesses; forming a spacer layer covering sidewalls of portions of the first semiconductor layers, while a bottommost one of the first semiconductor layers is uncovered by the spacer layer; etching the bottommost one of the first semiconductor layers to form a gap; forming a blocking dielectric in the gap; and forming source/drain epitaxy structures in the recesses and on opposite sides of the gate structure.


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