The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Mar. 30, 2023
Applied Materials, Inc., Santa Clara, CA (US);
Rahul Reddy Komatireddi, Bangalore, IN;
Rohith Cherikkallil, Bangalore, IN;
Sneha Rupa Kongara, Bangalore, IN;
Satwik Swarup Mishra, Bengaluru, IN;
Sachin Dangayach, San Jose, CA (US);
Si En Chan, Singapore, SG;
Remus Zhen Hui Koh, Singapore, SG;
Prayudi Lianto, Singapore, SG;
Yin Wei Lim, Singapore, SG;
Peng Suo, Singapore, SG;
Krishnaprasad Reddy Mallavaram, Bangalore, IN;
Khor Wui Cheng, Singapore, SG;
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
A method, apparatus and system for the automatic detection and measurement of chipping defects on diced wafers includes receiving an image of at least a portion of a diced wafer, aligning the received image of the at least the portion of the diced wafer, determining edges of the at least the portion of the diced wafer depicted in the aligned, received image, automatically determining at least one baseline from which to measure chipping defects on the at least the portion of the diced wafer from the determined edges, and measuring chipping defects on the at least the portion of the diced wafer using at least one determined, respective baseline. In some embodiments, the method, apparatus and system can further include applying a machine learning model to measured chipping defects to determine if a critical failure exists on the diced wafer.