The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Aug. 18, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Jingtao Xie, Wuhan, CN;

Bingjie Yan, Wuhan, CN;

Kun Zhang, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10W 20/20 (2026.01); H10W 42/00 (2026.01);
U.S. Cl.
CPC ...
H10W 42/121 (2026.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10W 20/20 (2026.01);
Abstract

A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.


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