Formation of low-temperature and high-temperature in-situ doped source and drain epitaxy using selective heating for wrap-around contact and vertically stacked device architectures

Abstract

Techniques herein provide thermal processing solutions applicable to both existing FINFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistor and gate-on-gate monolithic or heterogeneous CFET. Techniques include heating or annealing a first target material without heating or affecting performance of a second material or other materials. Techniques include using a first heating process to heat a substrate and materials provided thereon to a first temperature, and then using a wavelength/frequency tunable second heating process to increase temperature of the target material without increasing temperature of the second material or other materials.