The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Aug. 14, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Pei Lu, Hsinchu City, TW;

Shin-Yi Yang, New Taipei City, TW;

Yun-Chi Chiang, Hsinchu City, TW;

Han-Tang Hung, Taipei City, TW;

Cian-Yu Chen, Taichung City, TW;

Ming-Han Lee, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10W 20/00 (2026.01); H10W 20/42 (2026.01); H10W 20/44 (2026.01); H10W 20/40 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6219 (2025.01); H10D 64/251 (2025.01); H10D 64/254 (2025.01); H10D 84/0149 (2025.01); H10W 20/0261 (2026.01); H10W 20/069 (2026.01); H10W 20/42 (2026.01); H10W 20/4403 (2026.01); H10W 20/40 (2026.01);
Abstract

A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.


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