The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Jan. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ta-Chun Lin, Hsinchu, TW;

Jhon-Jhy Liaw, Zhudong Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/258 (2025.01); H10D 84/0179 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01);
Abstract

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes forming a dummy gate stack extending across a portion of the fin structure and forming gate spacers over sidewalls of the dummy gate stack. The gate spacers extend across portions of the fin structure. The method further includes removing the dummy gate stack to form a trench exposing the portion of the fin structure and trimming the semiconductor layers exposed by the trench. Each of the semiconductor layers covered by the gate spacers becomes wider than each of the semiconductor layers that is trimmed. In addition, the method includes removing the sacrificial layers and forming a metal gate stack wrapped around the semiconductor layers.


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