The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Sep. 24, 2020
Applicants:

Kwansei Gakuin Educational Foundation, Hyogo, JP;

Toyota Tsusho Corporation, Nagoya, JP;

Inventor:

Tadaaki Kaneko, Sanda, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C30B 29/36 (2006.01); C30B 23/06 (2006.01); H10D 62/832 (2025.01); H10P 14/20 (2026.01); H10P 14/22 (2026.01);
U.S. Cl.
CPC ...
C30B 29/36 (2013.01); C30B 23/06 (2013.01); H10D 62/8325 (2025.01); H10P 14/22 (2026.01); H10P 14/2904 (2026.01); H10P 14/2926 (2026.01); H10P 14/3208 (2026.01); H10P 14/3408 (2026.01); H10P 14/36 (2026.01);
Abstract

The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layerhaving a doping concentration of at least 1×10cm. As a result of comprising a dislocation conversion layerhaving this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.


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