The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Feb. 13, 2023
Applicant:

Chipbond Technology Corporation, Hsinchu, TW;

Inventors:

Sheng-Jen Wu, Hsinchu County, TW;

Shih-Chung Chang, Taichung City, TW;

Hsueh-Shun Yeh, Hsinchu County, TW;

Chun-Te Lee, Hsinchu County, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 11/408 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10W 72/30 (2026.01); H10W 72/59 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 72/334 (2026.01); H10W 72/344 (2026.01); H10W 72/352 (2026.01); H10W 72/383 (2026.01); H10W 72/59 (2026.01); H10W 72/934 (2026.01); H10W 72/952 (2026.01); H10W 90/734 (2026.01);
Abstract

A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.


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