The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jul. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ting-Li Yang, Tainan City, TW;

PO-Hao Tsai, Zhongli City, TW;

Ching-Wen Hsiao, Hsinchu, TW;

Hong-Seng Shue, Zhubei City, TW;

Ming-Da Cheng, Taoyuan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/20 (2026.01); H10W 20/00 (2026.01); H10W 20/40 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 72/20 (2026.01); H10W 20/089 (2026.01); H10W 20/42 (2026.01); H10W 20/435 (2026.01); H10W 20/496 (2026.01); H10W 72/01208 (2026.01); H10W 72/221 (2026.01);
Abstract

A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.


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