The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 29, 2022
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Bernhard Grote, Phoenix, AZ (US);

Jie Hu, Chandler, AZ (US);

Philippe Renaud, Chandler, AZ (US);

Congyong Zhu, Gilbert, AZ (US);

Bruce Mcrae Green, Gilbert, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 64/00 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 64/111 (2025.01); H10D 64/258 (2025.01); H10D 64/411 (2025.01); H10D 64/518 (2025.01); H10D 62/824 (2025.01);
Abstract

A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.


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