The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 22, 2022
Applicant:

Zhuhai Access Semiconductor Co., Ltd., Zhuhai City, CN;

Inventors:

Xianming Chen, Zhuhai City, CN;

Lei Feng, Zhuhai City, CN;

Benxia Huang, Zhuhai City, CN;

Wenjian Lin, Zhuhai City, CN;

Gao Huang, Zhuhai City, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/46 (2006.01); H05K 1/185 (2026.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4644 (2013.01); H05K 1/185 (2013.01); H05K 3/0047 (2013.01); H05K 3/4697 (2013.01);
Abstract

A method for manufacturing a packaging substrate, and a packaging substrate are disclosed. The method includes: providing a bottom board with a first circuit layer, the first circuit layer being provided with at least one demand point, and one side of the demand point being provided with a first to-be-avoided region; machining a first intermediate insulating layer on the bottom board, the first intermediate insulating layer including a first intermediate insulating dielectric covering the first to-be-avoided region; machining a first intermediate wiring layer on the first intermediate insulating layer, the first intermediate wiring layer including a first intermediate circuit partially arranged on the first intermediate insulating dielectric and connected to the demand point; machining a first insulating layer on the first intermediate wiring layer which is stacked on the bottom board and covers the first intermediate wiring layer; and machining a circuit build-up layer on the first insulating layer.


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