The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Feb. 17, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kelvin Tan Aik Boo, Singapore, SG;

Hong Wan Ng, Singapore, SG;

Seng Kim Ye, Singapore, SG;

Chin Hui Chong, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10B 80/00 (2023.01); H10W 70/05 (2026.01); H10W 70/62 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10B 80/00 (2023.02); H10W 70/093 (2026.01); H10W 70/641 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 72/865 (2026.01); H10W 72/884 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

Semiconductor device assemblies having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device assembly includes a substrate, a controller, and an interposer. The substrate has a top surface and a bottom surface. A cavity extends below the top surface. The controller has a first pin-out pattern. The interposer has a top surface with the first pin-out pattern that is directly connected to the controller and a bottom surface that has a second pin-out pattern. The interposer interconnects the first and second pin-out patterns, and the interposer and the second pin-out pattern are configured to be directly attached to a surface of the substrate in the cavity.


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