Fet fin and vertical nanosheet formation using porous semiconductors

Abstract

Structures and corresponding methods of fabrication for ICs having fins and/or vertical nanosheets made by forming and etching a porous semiconductor (π-Semi) from a crystalline semiconductor. Embodiments include FinFETs and 'gate-all-around' FETs. Such FET structures may be made by patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a fin or nanosheet; converting the outlined regions to π-Semi having essentially vertical walls; further converting the outlined regions to π-Semi having flared walls; then selecting one of these options: etching the π-Semi to define fins, etching the π-Semi to define nanosheets with a residual π-Semi floor, or etching the π-Semi to define nanosheets with no residual π-Semi floor; and forming a gate structure over the fins or around the nanosheets. Additional steps and structures (e.g., formation of source and drain regions, formation of contacts, metallization layers, vias, etc.) may then be performed.