The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Dec. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeremy D. Ecton, Gilbert, AZ (US);

Brandon Christian Marin, Gilbert, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Gang Duan, Chandler, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 20/20 (2026.01); H10W 40/70 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 20/20 (2026.01); H10W 40/70 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); H10W 90/792 (2026.01);
Abstract

Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.


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