The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

May. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ruei-Jyun Hsu, Hsinchu City, TW;

Wei Wang, Taipei City, TW;

Wei-Jen Chang, Miaoli County, TW;

Chung-Shi Chiang, Hsinchu County, TW;

Chia-Chi Ho, Hsinchu County, TW;

Hsin-Shan Liu, Changhua County, TW;

Chang-Hung Yu, Taipei City, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10P 74/00 (2026.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10W 20/42 (2026.01); H10W 42/00 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10P 74/273 (2026.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/127 (2025.01); H10W 20/42 (2026.01); H10W 42/00 (2026.01); H10W 74/137 (2026.01);
Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes: a substrate including a transistor, wherein the semiconductor device is surrounded by a seal ring; an interconnect structure over the transistor; a recess on a sidewall of the seal ring; a test pad in the interconnect structure, wherein the test pad extends from the interconnect structure to the recess of the seal ring.


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