The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Jun. 10, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shao-Ming Koh, Hsinchu City, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu City, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10P 50/00 (2026.01); H10P 50/24 (2026.01); H10P 50/28 (2026.01); H10P 50/64 (2026.01); H10P 70/00 (2026.01); H10W 20/00 (2026.01); H10W 20/40 (2026.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/822 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/797 (2025.01); H10D 64/0113 (2026.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10P 50/00 (2026.01); H10P 50/242 (2026.01); H10P 50/282 (2026.01); H10P 50/287 (2026.01); H10P 50/644 (2026.01); H10P 70/20 (2026.01); H10W 20/071 (2026.01); H10W 20/40 (2026.01); H10D 30/0212 (2025.01); H10D 30/6219 (2025.01); H10D 62/822 (2025.01);
Abstract

A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.


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