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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12672327 B1

PDFFull Text
Date of Patent:
Jun. 30, 2026

Filed:

Jul. 20, 2022

Electronic devices comprising pillars extending through a semiconductor material and adjacent to a source implant region, and related electronic systems and methods

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Collin Howder, Boise, ID (US);

Alyssa N. Scarbrough, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

TraskBritt

Primary Examiner:

William B Partridge

Assistant Examiner:

Gustavo G Ramallo

Int. Cl.
CPC ...
H10B 43/35 (2023.01); H10B 43/10 (2023.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10D 64/252 (2025.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02); H10D 30/0413 (2025.01); H10D 30/693 (2025.01); H10D 64/037 (2025.01);
Abstract

Electronic devices comprising a source stack comprising one or more conductive materials, a source implant region within a top portion of the source stack, a source contact adjacent to the source stack, sidewalls of the source contact vertically adjacent to the source implant region, a doped semiconductive material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped semiconductive material, and pillars extending through the tiers, the doped semiconductive material, and the source contact and into the source stack. Additional electronic devices are also disclosed, as are related methods and electronic systems.

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