The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2026
Filed:
Sep. 01, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Shantanu Telharkar, San Jose, CA (US);
Sheng-Shiung Wu, Pleasanton, CA (US);
Raju Joshi, Los Altos, CA (US);
Vasant Ramabadran, San Jose, CA (US);
Suresh Gopalrathnam, Los Altos, CA (US);
Anand Gupta, Ghaziabad, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware ('Debug FPGA') that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.