The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Feb. 26, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

PO-Han Wang, Hsinchu, TW;

Hung-Jui Kuo, Hsinchu, TW;

Yu-Hsiang Hu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10P 14/47 (2026.01); H10P 72/70 (2026.01); H10W 20/00 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 70/00 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/00 (2026.01); H10W 90/20 (2026.01); H10W 90/28 (2026.01);
U.S. Cl.
CPC ...
H10W 70/614 (2026.01); H10P 14/47 (2026.01); H10P 72/74 (2026.01); H10W 20/043 (2026.01); H10W 20/057 (2026.01); H10W 20/077 (2026.01); H10W 20/081 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 74/01 (2026.01); H10W 74/019 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10P 72/7418 (2026.01); H10P 72/7424 (2026.01); H10P 72/743 (2026.01); H10P 72/7436 (2026.01); H10W 70/099 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/0198 (2026.01); H10W 72/073 (2026.01); H10W 72/241 (2026.01); H10W 72/874 (2026.01); H10W 72/884 (2026.01); H10W 72/9413 (2026.01); H10W 74/00 (2026.01); H10W 90/28 (2026.01); H10W 90/291 (2026.01); H10W 90/722 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.


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