The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

May. 12, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tzu-Yu Chen, Kaohsiung City, TW;

Wen-Ting Chu, Kaohsiung City, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Sheng-Hung Shih, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/42 (2026.01); H10B 51/30 (2023.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10B 51/30 (2023.02); H10W 20/033 (2026.01); H10W 20/062 (2026.01); H10W 20/075 (2026.01); H10W 20/081 (2026.01); H10W 20/435 (2026.01);
Abstract

Some embodiments relate to a method of forming an integrated chip, including forming a first wire level over a substrate; depositing an etch stop layer over the first wire level; etching the etch stop layer to form an opening over the first wire level; depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening; depositing a first conductive layer over the barrier layer and in the opening; performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer; depositing a data storage layer and a second conductive layer over the first conductive layer; and patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.


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