Stacked transistor backside contact formation

Abstract

A semiconductor IC structure includes a dielectric contact liner between an upper S/D region backside contact and a lower S/D region. As a result of the dielectric contact liner, the overlap between the upper transistor and the lower transistor may be increased, which may lead to further device scaling. To achieve these benefits, material that later forms the dielectric contact liner is deposited within an associated upper S/D region backside contact opening and has etch selectivity that may result in a later self-aligned reformation of the backside contact opening with reduced risk of that opening extending into the neighboring lower S/D region. The ability to self-align the formation of the backside contact opening may allow for the placement of such opening to be relatively closer to lower S/D region. The dielectric contact liner material may remain between and adequately electrically isolate the backside contact and the lower S/D region.