Integration of discrete embeddable capacitors on integrated circuit chips

Abstract

Single-chip solutions and related methods that result in much higher capacitance densities than is achievable with current on-chip solutions and which reduce consumption of planar area of a mounting structure. Embodiments of the present invention use vertical stacking to affix one or more discrete embeddable capacitors to an IC chip superstructure or base structure, and either sequentially or concurrently form electrical connections between the discrete embeddable capacitors and the IC chip. The inventive processes are compatible with CMOS fabrication temperatures for the IC chip while allowing use of capacitors that are fabricated using other processes that may involve much higher temperatures. The inventive processes allow connection of relatively large capacitances (e.g., ˜0.5 μF-1 μF) to an IC chip without increasing the 2-D footprint of the IC chip. Some embodiments include reconfigurable discrete/affixed capacitors and/or discrete/affixed capacitors with through-vias (distinct from capacitor electrode connections) for connecting circuitry.