The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Sep. 20, 2021
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Bernd Schmoelzer, Radenthein, AT;

Edward Fuergut, Dasing, DE;

Ivan Nikitin, Regensburg, DE;

Wolfgang Scholz, Olching, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10W 20/20 (2026.01); H10W 74/01 (2026.01); H10W 74/47 (2026.01); H05K 1/185 (2026.01);
U.S. Cl.
CPC ...
H10W 74/147 (2026.01); H10W 20/20 (2026.01); H10W 74/017 (2026.01); H10W 74/127 (2026.01); H10W 74/134 (2026.01); H10W 74/47 (2026.01); H05K 1/186 (2013.01);
Abstract

A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.


Find Patent Forward Citations

Loading…