The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Dec. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard P. Guler, Hillsboro, OR (US);

Jeffrey S. Leib, Beaverton, OR (US);

Chanaka D. Munasinghe, Portland, OR (US);

Charles H. Wallace, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Mohit K. Haran, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10W 20/427 (2026.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01);
Abstract

Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.


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