The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Apr. 18, 2023
Applicant:

Utac Headquarters Pte. Ltd., Singapore, SG;

Inventors:

Il Kwon Shim, Singapore, SG;

Ronnie M. De Villa, Singapore, SG;

Dzafir Bin Mohd Shariff, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 72/29 (2026.01); H10W 74/10 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/652 (2026.01); H10W 70/66 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 90/10 (2026.01);
U.S. Cl.
CPC ...
H10W 74/137 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 72/29 (2026.01); H10W 74/141 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/652 (2026.01); H10W 70/66 (2026.01); H10W 72/01935 (2026.01); H10W 72/252 (2026.01); H10W 72/9223 (2026.01); H10W 72/923 (2026.01); H10W 72/934 (2026.01); H10W 72/9415 (2026.01); H10W 72/942 (2026.01); H10W 72/952 (2026.01); H10W 90/10 (2026.01);
Abstract

A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.


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