The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

May. 16, 2023
Applicant:

Zhuhai Yuexin Semiconductor Limited Liability Company, Zhuhai, CN;

Inventors:

Xianming Chen, Zhuhai, CN;

Yejie Hong, Zhuhai, CN;

Benxia Huang, Zhuhai, CN;

Gao Huang, Zhuhai, CN;

Xiaofeng Deng, Zhuhai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 20/00 (2026.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 20/01 (2026.01); H10W 70/095 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
Abstract

A packaging structure for realizing chip interconnection includes a core layer, a bridging layer, a first dielectric layer, a second dielectric layer, a first bonding pad layer and a second bonding pad layer. The first dielectric layer is arranged between the core layer and the first bonding pad layer, the second dielectric layer is arranged between the second bonding pad layer and the core layer. The first bonding pad layer is connected with the core layer through a first via, the second bonding pad layer is connected with the core layer through a second via. The bridging layer is embedded in the first dielectric layer. The bridging layer is electrically insulated from the core layer, and the bridging layer is connected with the first bonding pad layer through a third via.


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