The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jun. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Tainan City, TW;

Kun-Tsang Chuang, Miaoli City, TW;

Hsin-Chi Chen, Tainan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H10B 41/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 62/115 (2025.01); H10B 41/35 (2023.02); H10D 30/0411 (2025.01); H10D 30/68 (2025.01); H10D 64/021 (2025.01);
Abstract

A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.


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