The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Apr. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Pushkar Ranade, San Jose, CA (US);

Willy Rachmady, Beaverton, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 23/473 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 84/08 (2025.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01); H10W 40/47 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6706 (2025.01); H10D 30/021 (2025.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6741 (2025.01); H10D 30/675 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/08 (2025.01); H10D 84/85 (2025.01); H10P 14/3411 (2026.01); H10P 14/3421 (2026.01); H10P 14/3452 (2026.01); H10W 40/47 (2026.01);
Abstract

Integrated circuit (IC) including transistors with high-mobility/high-saturation velocity, non-silicon channel materials coupled to a silicon substrate through counter-doped sub-channel materials, which greatly reduce electrical leakage currents through the substrate when the IC is operated at very low temperatures (e.g., below −25 C). With low temperature operation, high transistor performance associated with the non-silicon channel materials can be integrated into high density IC architectures that avoid the limitations associated with semiconductor material layer transfers.


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