The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Mar. 21, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jan Proschwitz, Riesa SN, DE;

Sonja Koller, Bavaria, DE;

Thomas Wagner, Regelsbach, DE;

Vishnu Prasad, Munich, DE;

Wolfgang Molzer, Ottobrunn, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01K 3/30 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H05K 1/02 (2006.01); H05K 1/18 (2026.01); H05K 1/181 (2026.01); H05K 3/303 (2026.01); H10W 70/68 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 90/22 (2026.01);
U.S. Cl.
CPC ...
H05K 1/0284 (2013.01); H05K 1/181 (2013.01); H05K 3/305 (2013.01); H10W 70/68 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); H05K 2201/09072 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/1053 (2013.01); H05K 2201/10734 (2013.01); H10W 70/682 (2026.01); H10W 72/072 (2026.01); H10W 72/07236 (2026.01); H10W 72/07254 (2026.01); H10W 72/241 (2026.01); H10W 72/247 (2026.01); H10W 90/22 (2026.01); H10W 90/701 (2026.01); H10W 90/721 (2026.01); H10W 90/724 (2026.01);
Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.


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