The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jul. 31, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Eric N. Lee, San Jose, CA (US);

Violante Moschiano, Avezzano, IT;

Jeffrey S. Mcneil, Nampa, ID (US);

James Fitzpatrick, Laguna Niguel, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Patrick R. Khayat, San Diego, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 2207/2254 (2013.01);
Abstract

Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.


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