The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Mar. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Pushkar Ranade, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/20 (2026.01); H10B 12/00 (2023.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10B 12/50 (2023.02); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 72/823 (2026.01); H10W 90/297 (2026.01);
Abstract

In one embodiment, an apparatus includes a first die adapted on a second die. The first die may have a plurality of cores, each of the plurality of cores associated with a first plurality of through silicon vias (TSVs), and the second die may have dynamic random access memory (DRAM). The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs. Other embodiments are described and claimed.


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