Memory device and operation method thereof

Abstract

In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuit is configured to program the target memory cell, perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell, configure one or more verification parameters of the target memory cell based on the first sample value, perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell, and configure one or more read parameters of the target memory cell based on the second sample value.